1. Field of the Invention
This invention relates generally to integrated circuits memory devices, and more particularly to an improved apparatus and method for generating data background patterns used for testing random access memories.
2. Background of the Invention
Random access memories (RAMs) are typically tested using an external test machine, such as a state machine, or a built-in-self-test (BIST) machine that provides predefined patterns able to identify faulty memory cells of the memory array. Testing aids in the discovery of certain faulty cells and is key to the proper characterization of the RAM. For both the external test machine and the BIST machine cases the predefined patterns are defined by engineers and can be considered sufficiently discriminatory to provide an adequate information concerning the state of one or more memory cells, whether it be a good, repairable, or fail state, for instance. A predefined testing pattern may be thought of as having two parts. The first part includes the commands, such as read, write, wait, etc., for testing the memory cells and the addresses of the memory cells to be tested. The second part of a predefined pattern is the pattern itself comprised of the data pattern and the background pattern.
So-called xe2x80x9cmarchxe2x80x9d patterns are commonly used to test RAM memories. There are many different march patterns available for testing memories; a few march patterns commonly used to test memories include MATS, MATS+, MATS++, MARCHX, MARCHC-, MARCHA, MARCHY, MARCHB, MARCHLR, MARINESCU. Not all march testing patterns detect all faults of a RAM and thus different types of march testing patterns are used to detect different RAM faults. Some types of march patterns are designed to target specific types of faults while others seek to identify as many faults as possible. The various types of faults that can be identified by march testing patterns include stuck at faults (SAFs), transition faults (TFs), coupling faults (CFs), address decoder faults (AFs), state coupling faults (SCFs), and bridging faults (BFs). The common characteristic of all march patterns, however, is that a sequence of events, such as reads and writes, for instance, are applied to one address of the memory array before moving onto the next address of the memory array being tested. This testing sequence is repeated in an ascending or descending order, as dictated by the particular march algorithm, throughout the address space being tested.
The testing of word-oriented memories which have more than 1-bit per word present a special testing problem. In a word-oriented memory, allowances have to be made to the traditional march patterns in order to accommodate the detection of a special set of faults, called intraword faults, that exist between two or more bits of a word in a memory array. Typically intraword faults are identified by applying traditional march patterns to a word-oriented memory and repeating the test the required number of times using multiple data backgrounds, where the data background refers to the data applied to a complete word. As an example, consider the following simple sequence of a march pattern:
/{w0r0w1r1}
which means to xe2x80x9cwrite zero, read zero, write 1, read 1xe2x80x9d starting at the lowest memory address and progressing to the highest memory address of the memory array to be tested. This sequence is very straightforward for a single-bit-wide memory, but is more complex for a word-oriented memory in which the xe2x80x980xe2x80x99 means xe2x80x9cdata backgroundxe2x80x9d and the xe2x80x981xe2x80x99 means xe2x80x9cinverted data background.xe2x80x9d So, xe2x80x980xe2x80x99 might be represented by any of the following data background patterns: 00000000, 01010101, 00110011, 00001111; xe2x80x981xe2x80x99 would be represented by the inverse of these data background patterns. To apply these background patterns, the marching pattern algorithm would be repeated using each of these background patterns in place of the xe2x80x981xe2x80x99 or xe2x80x980xe2x80x99 in the above sequence. Thus for an 8-bit wide memory there are 256 possible data backgrounds implicated by this sequence. Typically, however, only log2N+1 data backgrounds, where N refers to the number of bits per word, are used in order to help reduce testing time.
Compounding the complexity of testing word-oriented memories is the ever-increasing width of the data bus of the memory array. Current data bus widths of memory devices are 64 bits and data bus widths upwards of 256/512 bits are expected in the near future. The increased width of the data bus is exponential in nature, doubling about every 9 to 10 months or so. In the case of an external test machine, such increased data bus widths cannot be easily handled by an external tester because the number of package pins is strictly limited by the application. For instance, a package housing a memory array device might have only 100 to 200 pins, a number of pins insufficient to handle testing a data bus having a width of 256 or 512 bits.
The internal BIST machine solution, while it does not have this pin-out limitation, is a problematic solution in its own right. With the always increasing width of the data bus, the BIST machine that provides patterns and backgrounds becomes more and more complex, each individual data needing a driver and more complex algorithms to properly test the memory. The number of gates of the BIST machine can be expected to increase at least at the same rate of increase of the data bus width, if not more, as the number of requested data backgrounds required to completely test the memory array may increase more rapidly. In order for the BIST solution to support greatly expanded data bus widths, a large number of signals which occupy a large area of the routing channel of the memory is called for. Moreover, the BIST machine solution is a solid-state solution embedded in the silicon of the memory array device and is therefore inherently inflexible with regard to the type of patterns that it employs to test the memory array. The BIST machine is hard to modify should a pattern be missing Using the BIST solution, it is impossible to later add a xe2x80x9cforgottenxe2x80x9d pattern without fabricating a new maskset for the BIST circuitry since the BIST solution is embedded in silicon.
Referring to FIG. 1, a block diagram illustrates a possible scenario for testing an embedded memory array that is controlled by a controller of the device on which the memory is embedded. The data patterns for testing the memory are provided by a test machine which may be either a BIST machine or an external test machine, as discussed above. The testing data provided by the test machine is multiplexed with information from the controller as shown. Information from the memory array is likewise multiplexed before being provided to the controller that in turn provides the results of the memory testing to the test machine. The greatly increased number of gates required in the test machine, particularly if the test machine is a BIST machine, as well as the number of multiplexers required to adequately test RAMs having ever-increasing data bus widths can serious degrade device performance. These increased demands in silicon are evidenced by the great number of wires, or routing, that is illustrated between the test machine and the multiplexer circuitry, between the multiplexer circuitry and the memory array, and between the multiplexer circuitry and the controller.
From the foregoing description, it can be seen that there is a need in the art to have an improved method and structure for the testing of RAMs. The improved method and structure should accommodate testing of RAMs having ever-increasing data bus widths by both BIST machines and external test machines. The number of additional package pins and additional silicon of the RAM should be kept to a minimum while providing for maximum testing flexibility.
According to the principles of the present invention, an improved apparatus and method for generating data background patterns for testing random-access-memories is provided. The improved apparatus of the present invention includes circuitry of a RAM that comprises a programming element and a selection element. The programming element is able to selectively program desired bits of a data background pattern according to a programming information signal provided to the RAM in order to generate a programmed data background pattern. The selection element receives the programmed data background pattern as well as a normal, application data and selects and outputs to an input/output buffer of the RAM either the programmed data background pattern or application data according to the logic state of a test control signal. There is one placement per data bit of the data background pattern of circuitry that accomplishes the mandates of the programming and selection elements. According to a preferred embodiment of the present invention, for each data bit of the data background pattern the programming element comprises a shift register element that receives a programming information signal and a clock signal and shifts in and outputs the programming information signal in accordance with the clock signal and a logic element that receives the programming information signal from the shift register and a data bit of a data background pattern and performs an exclusive-or (XOR) function on the programming information signal and the data bit of the data background pattern to generate a programmed data bit. For each data bit of the data background pattern the selection element comprises a multiplexer element controlled by a test control signal that receives an application data bit and the programmed data bit, wherein when the test control signal is a first logic state indicative of a testing mode of the RAM the multiplexer element selects and outputs the programmed data bit to an input/output buffer of the RAM and when the test control signal is a second logic state indicative of a normal operating mode of the RAM the multiplexer element selects and outputs the application data bit to the input/output buffer of the RAM.
The methodology of the present invention accomplishes the goal of programmability of data background patterns used to test a RAM by providing a data background pattern to the RAM, providing a programming information signal to the RAM, selectively programming the data bits of the data background pattern in accordance with the programming information signal to generate a programmed test data pattern, and providing the programmed test data pattern to an input/output buffer of the RAM when the RAM is in a testing mode as indicated by a test control signal. The methodology is further capable of providing an application data to the input/output data when the RAM is in a normal operating mode as indicated by the test control signal. According to the preferred embodiment of the invention, the programming information signal is provided to the RAM by using a shift register to shift in this information and programmability of the various bits of the data background pattern are programmed using an exclusive-OR (XOR) gating function that receives the programming information signal and an appropriate bit of the data background pattern. Of course, one skilled in the art may accomplish the methodology of the present invention using a different structure on the RAM so long as the functionality of the methodology is accomplished.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.